PC-104 Specifications

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This specification is subject to change without notice. While every effort has been made to ensure the accuracy of the material contained within this document, the PC/104 Consortium shall under no circumstances be liable for incidental or consequential damages or related expenses resulting from the use of this specification. If errors are found, please notify the PC/104 Consortium.

PC/104 is a trademark of the PC/104 Consortium. All other marks are the property of their respective companies.


REVISION HISTORY

Version 1.0, March 1992 - Initial release.

Version 2.1, July 1994 - Revised specification incorporating changes to conform with IEEE P996.1 draft version D1.00:

  • Changed bus options. Eliminated the "option 2" configurations having right-angle P1 and P2 connectors. Created new "option 2" configurations similar to "option 1," but without the stackthrough pins. Added a statement indicating that a P2 connector may be included on 8-bit modules, if desired.
  • Added two additional mounting holes to 8-bit bus versions, making the mounting hole patterns of both 8- and 16-bit modules identical.
  • Added an I/O connector region along the bus edge of the module.
  • Increased widths of I/O mating-connector regions from 0.4" to 0.5".
  • Changed lengths of I/O mating-connector regions so that their edges align with the outer edges of the annular rings of adjacent mounting holes.
  • Reduced the bus drive requirement on the signals that had been specified at 6 mA to 4 mA.
  • Added specification of module power requirements.
  • In Appendix C, Section 3, changed minimum value of pullup resistance on shared interrupt line from 10K to 15K ohms.
  • Added a section defining levels of PC/104 conformance.
Version 2.2, September 1994
  • Added correction sheet showing revised schematic for Appendix C.
Version 2.3, June 1996
  • Incorporated correction to Appendix C schematic.
  • Changed P2 connector Pin 1 designation in 16-bit module dimension drawings.
  • Added metric dimensions, including metric versions of module dimension drawings.
  • Minor formatting changes.

TABLE OF CONTENTS

	1. INTRODUCTION

	2. MECHANICAL SPECIFICATIONS	
	2.1  Module Dimensions	
	2.2  Bus Options	

	3. ELECTRICAL SPECIFICATIONS	
	3.1  Signal Functions and Assignments	
		3.1.1  Signal Definitions	
		3.1.2  Signal Assignments	
		3.1.3  Added Grounds	
		3.1.4  Key Locations	
	3.2  AC Signal Timing	
	3.3  DC Signal Levels	
	3.4  Bus Drive Current	
	3.5  Interrupt-Sharing Option	
	3.6  Bus Termination Option	
	3.7  Module Power Requirements	

	4. LEVELS OF CONFORMANCE
	4.1  PC/104 "Compliant"	
	4.2  PC/104 "Bus-compatible"	

	APPENDICES
	A.   Module Dimensions	A-1
		A.1  PC/104 8-Bit Module Dimensions (English)	
		A.2  PC/104 8-Bit Module Dimensions (Metric)	
		A.3  PC/104 16-bit Module Dimensions (English)	
		A.4  PC/104 16-bit Module Dimensions (Metric)	
	B.   Bus Signal Assignments	
	C.   Interrupt-Sharing Option	
		C.1  Introduction	
		C.2  Recommended Circuit	
		C.3  Restrictions	
		C.4  "P996 Compatibility" Option Jumper	

1. INTRODUCTION

While the PC and PC/AT architectures have become extremely popular in both general purpose (desktop) and dedicated (non-desktop) applications, its use in embedded microcomputer applications has been limited due to the large size of standard PC and PC/AT motherboards and expansion cards.

This document supplies the mechanical and electrical specifications for a compact version of the IEEE P996 (PC and PC/AT) bus, optimized for the unique requirements of embedded systems applications. The specification is herein referred to as "PC/104", based on the 104 signal contacts on the two bus connectors (64 pins on P1, plus 40 pins on P2).

Briefly, the needs of embedded applications have been satisfied by PC/104, through the following key differences from standard P996:

  • Reducing the form-factor, to 3.550 by 3.775 inches (90 by 96 mm).
  • Eliminating the need for backplanes or card cages, through its self-stacking bus.
  • Minimizing component count and power consumption (to typically 1-2 Watts per module), by reducing required bus drive on most signals to 4 mA.
PC/104 specifies two module versions 8-bit and 16-bit which correspond to the PC and PC/AT bus implementations, respectively.

The remainder of this specification covers the differences from the IEEE P996 draft standard. Designers of modules and systems based on PC/104 should be familiar with the IEEE P996 specification, which is available from:

IEEE Standards Office
445 Hoes Lane
Piscataway, NJ 08854

If errors are found in this document, please send a written copy of the suggested corrections to:

PC/104 Consortium
849B Independence Ave
Mountain View, CA 94043


2. MECHANICAL SPECIFICATIONS

2.1 Module Dimensions

PC/104 modules can be of two bus types, 8-bit and 16-bit. These correspond to the PC and PC/AT buses, respectively. The detailed mechanical dimensions of these two PC/104 bus types are provided in Appendix A.

2.2 Bus Options

As shown in the figures in Appendix A, each of the two bus types (8-bit and 16-bit) offers two bus options, according to whether or not the P1 and P2 bus connectors extend through the module as "stackthrough" connectors. These options are are provided to help meet the tight space requirements of embedded applications.

Figure 1 illustrates a typical module stack including both 8- and 16-bit modules, and shows the use of both the "stackthrough" and "non-stackthrough" bus options. As shown in Figure 1, when 8- and 16-bit modules are combined in a stack, the 16-bit modules must be stacked below (i.e., on the "secondary side" of) the 8-bit modules. A "passive" P2 bus connector may optionally be included in the design of 8-bit modules, to allow the use of these modules anywhere in a stack.

Figure 1. Typical Module Stack


3. ELECTRICAL SPECIFICATIONS

3.1 Signal Functions and Assignments

    3.1.1 Signal Definitions

    All PC/104 bus signals are identical in definition and function to their P996 counterparts.

    3.1.2 Signal Assignments

    Signals are assigned in the same order as on the edgecard connectors of P996, but transformed to the corresponding header connector pins. Signal assignments for the J1/P1 and J2/P2 connectors are given in Appendix B.

    3.1.3 Added Grounds

    Several ground pins have been added, to maximize bus integrity. See Appendix B.

    3.1.4 Key Locations

    Key locations - consisting of omitted pins on P1 and P2, and plugged holes on J1 and J2 - have been designated on each bus connector, to help assure proper connector mating. See Appendix B.

3.2 AC Signal Timing

All PC/104 bus signals are identical in signal timing to their P996 counterparts.

3.3 DC Signal Levels

All PC/104 bus signal DC logic high and logic low voltage levels are identical to their P996 counterparts.

3.4 Bus Drive Current

To reduce component count and minimize power consumption and heat dissipation most bus signals have a reduced bus drive requirement of 4 mA. The exception is open collector driven signals which must drive 330 ohm pullup resistors defined by the P996 specification. This allows direct driving of the bus by many ASIC devices, and by HCT family logic.

Specifically, the following signals must be driven with devices capable of providing 20 mA sink current (as indicated in P996):

MEMCS16*
IOCS16*
MASTER*
ENDXFR*

All other signals may be driven with devices capable of providing 4 mA sink current.

3.5 Interrupt-Sharing Option

The P996 specification briefly mentions an optional means to share a single bus interrupt line among multiple interrupting devices. Appendix C provides a design guideline which can help ensure compatibility of interrupt-sharing among PC/104 modules.

3.6 Bus Termination Option

As in P996, termination of the PC/104 bus signals may be desired in some systems to increase data integrity and system reliability. When termination is included, AC termination networks must be used to provide termination close to the characteristic impedance of the signal lines without exceeding the DC output current capabilities of the drivers.

As in the P996 specification, the recommended network consists of a resistor-capacitor network of 40-60 ohms in series with 30-70 pF, connected between each bus signal and ground.

Whether termination is needed, and where it should be located, is dependent on the specific system configuration and must be determined by the system designer.

3.7 Module Power Requirements

The operating voltage range and maximum power requirements of each module are given in Table 1. Each module shall not draw more than the operating current indicated. The total power requirement of a PC/104 module stack is the sum of that required by each of the modules in the stack. Operating voltages, which refer to the voltage measured at the appropriate bus connector pins of any given module, are specified to 5 percent. Only those voltages required by modules in a system need be supplied to the bus.

Table 1. Module Power Requirements

Nominal Voltage Maximum Voltage Minimum Voltage Maximum Current
+12 Volts +12.6 Volts +11.4 Volts 1.0 Amp
+5 Voltss +5.25 Voltss +4.75 Voltss 2.0 Amp
-5 Voltss -4.75 Voltss -5.25 Voltss 0.2 Amp
-12 Voltss -11.4 Voltss -12.6 Voltss 0.3 Amp


4. LEVELS OF CONFORMANCE

This section provides terminology intended to assist manufacturers and users of PC/104 bus-compatible products in defining and specifying conformance with the PC/104 Specification.

4.1 PC/104 "Compliant"

This refers to "PC/104 form-factor" devices that conform to all non-optional aspects of the PC/104 Specification, including both mechanical and electrical specifications.

4.2 PC/104 "Bus-compatible"

This refers to devices which are not "PC/104 form-factor" (i.e., do not comply with the module dimensions of the PC/104 Specification), but provide a male or female PC/104 bus connector that meets both the mechanical and electrical specifications provided for the PC/104 bus connector.


APPENDIX A

MODULE DIMENSIONS


APPENDIX B

PC/104 Bus Signal Assignments

	Pin	J1/P1	J1/P1	J2/P2	J2/P2
	Number	Row A	Row B	Row C1	Row D1

	0	 --	 --	0V	0V
	1	IOCHCHK*	0V	SBHE* 	MEMCS16*
	2	SD7	RESETDRV	LA23  	IOCS16*
	3	SD6	+5V	LA22  	IRQ10
	4	SD5	IRQ9	LA21  	IRQ11
	5	SD4	-5V	LA20  	IRQ12
	6	SD3	DRQ2	LA19  	IRQ15
	7	SD2	-12V	LA18  	IRQ14
	8	SD1	ENDXFR*	LA17  	DACK0*
	9	SD0	+12V	MEMR* 	DRQ0
	10	IOCHRDY	(KEY)2	MEMW* 	DACK5*
	11	AEN	SMEMW*	SD8   	DRQ5
	12	SA19	SMEMR*	SD9   	DACK6*
	13	SA18	IOW*	SD10  	DRQ6
	14	SA17	IOR*	SD11  	DACK7*
	15	SA16	DACK3*	SD12  	DRQ7
	16	SA15	DRQ3	SD13	+5V
	17	SA14	DACK1*	SD14	MASTER*
	18	SA13	DRQ1	SD15	0V
	19	SA12	REFRESH*	(KEY)2	0V
	20	SA11	SYSCLK	 --	--
	21	SA10	IRQ7	 --	--
	22	SA9	IRQ6	 --	--
	23	SA8	IRQ5	 --	--
	24	SA7	IRQ4	 --	--
	25	SA6	IRQ3	 --	--
	26	SA5	DACK2*	 --	--
	27	SA4	TC	 --	--
	28	SA3	BALE	 --	--
	29	SA2	+5V	 --	--
	30	SA1	OSC	 --	--
	31	SA0	0V	 --	--
	32	0V	0V	 --	--
NOTES:
1. Rows C and D are not required on 8-bit modules. See Section 2.2.
2. B10 and C19 are key locations. See Section 3.1.4.
3. Signal timing and function are as specified in P996.
4. Signal source/sink current differ from P996 values. See Section 3.4.


APPENDIX C

INTERRUPT-SHARING OPTION

C.1 Introduction

The Interrupt Request lines (IRQn's) on the P996 bus are active high. Consequently, the usual technique of wire-ORing open-collector driven active low bus signals cannot be used for interrupt-sharing in the PC bus architecture.

The P996 specification briefly mentions an optional means to share a single bus interrupt line among multiple interrupting devices. This appendix provides design guidelines which can help assure compatibility of interrupt-sharing among PC/104 modules.

C.2 Recommended Circuit

A circuit similar to that shown in the figure below can provide interrupt-sharing of the active high IRQ signals on the P996 bus, given a few system-level restrictions (see below).

NOTE: This recommendation does not comply with the P996 specification, since it is not possible to implement interrupt-sharing in a P996 compatible manner.

Typical Interrupt-Sharing Circuit

C.3 Restrictions

All bus devices sharing a common interrupt must be equipped with a suitable interrupt-sharing circuit (see Figure, above) and must meet the following two restrictions:

The interrupt line being shared must not have a pullup resistance (to +5 volts) less than 15K ohms anywhere in the system. (Typically, the pullup resistance is located on the CPU module, so this is generally a restriction on the design of the CPU module.) Resistive bus termination will generally violate this restriction; use AC termination instead (Section 3.6).

The interrupt line being shared must have one (and only one) pulldown resistor (1K ohms) connected between the IRQ line and ground. Resistive bus termination will generally violate this restriction; use AC termination instead.

C.4 "P996 Compatibility" Option Jumper

The P996 specification calls for using a 2.2K pullup resistor on each of the IRQ lines, which violates the 15K minimum pullup resistance allowed with the recommended interrupt-sharing circuit. In systems having this value of pullup, devices with the circuit shown in the above figure can be made compatible by disabling their interrupt-sharing circuit. This is accomplished by unshorting both JP1 and JP2, resulting in a normal P996 (non-shared) interrupt configuration (but with the reduced bus drive common to other PC/104 bus signals).

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